(a) Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and in particular, to a nonvolatile semiconductor memory device of a type which enables an electrical erasure by a batch process.
(b) Description of the Related Art
Electrically erasable, programmable memory devices, known as EEPROMs, include a flash memory, which is a type of non-volatile memory enabling a batch erasure. Various structures have been proposed for the flash memory, and include one which is referred to as a virtual ground, split gate type. An EEPROM of this type has two features: (1) the source/drain of a memory cell is used as a buried bit line, and (2) selection transistors called "a split gate type" are connected in series in each memory cell. A conventional flash memory of this type is described, for example, in Patent Publication No. JP-A-1990-292870.
Referring to FIGS. 1 to 4, a typical conventional EEPROM of the virtual ground, split gate type will be described. FIG. 1 is a partial plan view of a cell array of a typical EEPROM of this type, while FIGS. 2 and 3 are sections taken along lines A--A and B--B, respectively, in FIG. 1.
As shown in FIGS. 1 to 3, a plurality of n.sup.+ -buried diffused layers 8, which constitute source/drain regions, are formed on the surface area of a p-silicon substrate 1, and extend in a column direction, i.e., in the vertical direction as viewed in FIG. 1. The n.sup.+ -buried diffused layer 8 is covered by a relatively thick silicon oxide film 9. Element separating insulator films or filed oxide films 2 are formed parallel to one other on the substrate 1, extending in a row direction, i,e, in the direction perpendicular to the buried diffused layers 8. A plurality of floating gates 4 made of polycrystalline silicon are formed in a matrix over the substrate 1, with a gate oxide film 3 being interposed therebetween, in a manner such that part of each of the floating gates 4 overlaps the buried diffused layer 8. A strip control gate 6 made of polycrystalline silicon is formed on top of the floating gate 4, with an intergate oxide film 5 being interposed therebetween, and extends in the row direction perpendicular to the buried diffused layer 8. The surface of the control gate 6 is covered by a silicon oxide film 7.
FIG. 4 shows an equivalent circuit diagram of the cell array shown in FIG. 1. As shown in FIG. 4, the n.sup.+ -buried diffused layers 8 constitute bit lines (B1, B2 . . . ), while the control gates 6 constitute word lines (W1, 2 . . . ). On top of the channel of each memory cell, there are a first portion over which the floating gate 4 and the control gate 6 are disposed in an overlapping relationship and a second portion where the control gate 6 directly opposes the channel, the second portion being a so-called split gate.
The memory operates as follows: A read operation for memory cell (1, 2), for example, i.e., memory cell in first column and second row in FIG. 9, takes place by applying 5 V, for example, to the word line W2, connecting the bit line B1 to the ground, applying 1.5 V to the bit line B2, connecting the remaining word lines W1, W3, W4 . . . to the ground, and leaving the remaining bit lines B3, B4 . . . in a floating state.
A programming operation to memory cell (1, 2) takes place by applying 12 V, for example, to the word line W2, connecting the bit line B1 to the ground, applying 7 V to the bit line B2, and connecting the remaining non-selected word lines W1, W3, W4 . . . to the ground, thus generating in the channel of the selected cell (1, 2) hot electrons which are injected into the floating gate of this cell.
An erase operation of the memory cells takes place by connecting the word line implemented by strip control gate 6 to the ground, and applying 15 V, for example, to the bit lines implemented by n.sup.+ -buried diffused layers 8, thus extracting carriers from the floating gates to the respective source/drain regions of the memory cells.
The conventional EEPROM as described above are manufactured by steps which are summarized below.
(1) Ions are selectively injected into the surface area of p-silicon substrate 1 to form n.sup.+ -buried diffused layer 8.
(2) A silicon oxide film is deposited by a CVD process, and configured in strip patterns extending perpendicular to the n.sup.+ -buried diffused layer 8, thus forming the field oxide films 2.
(3) Gate oxide film 3 is formed by thermal oxidation between the field oxide films 2.
(4) In order to form the floating gate 4, a first polycrystalline silicon film doped with phosphorus at a uniform concentration of 1 E 20/cm.sup.3 (1.times.10.sup.20 atoms/cm.sup.3) or greater is deposited, then configured to exhibit strip patterns which extend parallel to one another and to the n.sup.+ -buried diffused layer 8. The purpose of doping the polycrystalline silicon film with phosphorus, while the film is being formed, is to achieve a film of a uniform concentration over the entire film thickness, and the phosphorus is doped to a high concentration in order to enhance the etch rate and etch selectivity. The structure after the configuring of the first polycrystalline silicon is shown in a perspective view of FIG. 5. The strip polycrystalline silicon films 4a extend parallel to one another in the column direction, which is perpendicular to the field oxide films 2.
5) After formation of the intergate oxide film 5, a second polycrystalline silicon film is deposited and then configured in second strip films which extend parallel to one another and perpendicular to the n.sup.+ -buried diffused layer 8, thus forming the strip control gates 6 extending in the row direction. Subsequently, the first strip films 4a are patterned by using the strip control gate 6 to define separate floating gates 4 arranged in a matrix.
The conventional EEPROM as described above has a drawback in which erasure current or programming current fluctuates from cell to cell in operation of the flash memory, to thereby reduce the throughput of the flash memory.